1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, there is an constant demand for enhanced functionality of electronic devices which forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof.
However, with some modern devices, operating speed of complex integrated circuits is no longer limited by the switching speed of the individual transistor element, but rather by the electrical performance of the complex wiring system used in such an integrated circuit device. Such a wiring system may be formed above the device level and it may include the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level, on which the circuit elements are manufactured, but require the use of one or more additional metallization layers, which generally include metal-containing lines providing the inner level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These interconnect structures can be made of a variety of different materials, e.g., copper, tungsten, etc. and they provide the electrical connection to the various stacked metallization layers and the individual circuit elements.
Typically, an appropriate vertical contact structure is provided, which connects, on one end, to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors. The opposite end of the vertical contact is conductively coupled to a respective metal line in the metallization layer and/or to a contact region of a further semiconductor based circuit element, in which case the interconnect structure in the contact level is also referred to as local interconnect. The contact structure may comprise contact elements and/or contact plugs having a generally square or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. Upon further shrinkage of the critical dimensions of the circuit elements in the device level, the dimensions of metal lines, vias and contact elements also have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of the desired reliability of the integrated circuits. Consequently, in lower lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may be provided in order to achieve the required “packing density” in accordance with density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level have critical dimensions that are on that same order of magnitude. The contact elements typically represent cylindrically shaped plugs, which are formed of an appropriate metal or metal composition, such as tungsten, in combination with appropriate barrier materials. When forming tungsten-based contact elements, typically the interlayer dielectric material is formed first and is patterned to define a plurality of contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. In particular, in densely packed device regions, the lateral size of the drain and source areas and thus the available area for the contact regions may be 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy. In some cases, despite a manufacturer's best efforts, there are errors in forming the contact openings in the proper location. When the conductive contacts are formed in these misaligned openings, the performance of the resulting device may be degraded, if not destroyed.
As noted above, continued reduction in feature sizes, causes manufacturers to redesign process techniques and to develop new process strategies and tools so as to comply with the new design rules. For example, current-day planar transistors for use in a very sophisticated integrated circuit device may have gate lengths on the order of 15-25 nm, and the gate electrode structures of such an integrated circuit device may be formed with a gate pitch on the order of approximately 80 nm. As device dimension have continued to shrink over the years, it is becoming more and more difficult to precisely form the conductive contacts and to accurately position the metal line that connects to such contacts. More specifically, with the gate pitch at approximately 80 nm, it is very difficult to accurately locate a metal line to connect to the conductive contacts without also running the risk of the of a misaligned metal line shorting-out to a nearby gate electrode. Such inaccuracies can, at best, lead to reduced device performance and, at worst, to complete device failure. The aforementioned difficulties are anticipated to be even more problematic as device dimension continue to shrink. For example, if the gate pitch of a future generation of such integrated circuit devices is reduced to approximately 56 nm, then, all other things being equal, there may not be any margin for error or “process window” for forming such conductive contacts and metal lines.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.